Mitsubishi M54958 Dual-PLL Chip with Serial Input I encountered this chip in a lot of Panasonic's older wireless phones like the KX-T9X00 series. Its operating frequency seems to be up to 500 Mhz. In the wireless sets its working at 429/443 Mhz. Pin configuration: 1 - SI (Serial Input for Data) 2 - CPS (Clock Pulse for Serial Data) 3 - RST (Register Store) low while data is input, data will be transferred to the counters on rising edge. 4 - REF1 (Decoupling capacitor for Reference 1 to ground) typically 1 nF 5 - FIn1 (Frequency Input PLL 1 ) 6 - Lock1 (Lock Detect PLL 1) low signals PLL 1 locked. 7 - PD1 (Charge Pump PLL 1) 8 - LFI1 (Lowpass Filter Input PLL 1) 9 - LFO1 (Lowpass Filter Output PLL 1) 10 - Supply Ground 11 - P/N (Positive/Negative) High sets positive VCO frequency/voltage characteristics 12 - LFO2 ( Lowpass Filter Output PLL 2) 13 - LFI2 (Lowpass Filter Input PLL 2) 14 - PD2 (Charge Pump PLL 2) 15 - Lock2 (Lock Detect PLL 2) low signals PLL 2 locked. 16 - FIn2 (Frequency Input PLL 2 ) 17 - REF2 (Decoupling capacitor for Reference 2) 18 - Xout (Output for on-board Reference Oscillator) 19 - Xin (Input for onboard Reference Oscillator or from external Oscillator) 20 - Vcc (Positive Power Supply 3 to 5 Volts) Register description The M54958 chip consists of three counters where at least the two PLL counters have a range of 17 bits each for covering divider values up to 131072. A 21-bit word is used to control the PLL chip. The first 4 bits determine the counter to program and the operation of the PLL's. Switching off a PLL saves about 5 mA Supply Current. ******** Programming Model *************** Transmission start --------------------------------->> ____________________________________________________ | | | | | | | | | | | | | | 0 | 1 | 2 | 3 |MSB of divider..17 data bits to follow.......LSB ---------------------------------------------------- | | | | | | | | ( Program Control Bits) | | | ----: 00 - no counter to program (use this for PLL on/off switching) | | |-------: 01 - program PLL 1 | | 10 - program PLL 2 | | 11 - program reference counter | | | |-----------: (PLL 2 control bit) 0 is on , 1 is off | |---------------: (PLL 1 control bit) 0 is on , 1 is off ***************************************************** Data Input Method rough timing diagram for data input ____ _____ RST | | |_______________________________________________...______| _ _ _ _ _ _ _ _ _ CPS | | | | | | | | | | | | | | | | | | _____| |___| |___| |___| |___| |___| |___| |___| |__...__| |___ _____ _____ _____ _____ _____ _____ _____ _____ ..._____ SI XXXX PLL X PLL X Prg X Prg X MSB X D16 X D15 X D14 X D0 XXXX XXXX 1 X 2 X 2 X 1 X Div X X X X XXXX ----- ----- ----- ----- ----- ----- ----- ----- ...----- X = data may change Matthias Schoeldgen DC7UR 9/19/2006